chisel（一）初識(shí)

這個(gè)夏天，一個(gè)很奇妙的機(jī)會(huì)，突然觸碰到一個(gè)全新的東西，那就是Chisel。首先感謝 _iChthyosaur的博客 https://blog.csdn.net/qq_34291505/article/details/86744581給予的平臺(tái)讓我第一次接觸到這個(gè)新鮮的東西，我決定繼續(xù)開(kāi)始自己的學(xué)習(xí)之旅，這個(gè)系列的博客也不會(huì)是簡(jiǎn)單的轉(zhuǎn)述，還是有自己的思考，初次接觸一定還是會(huì)有很多理解上的問(wèn)題，希望大家共同討論共同進(jìn)步。

初次接觸Chisel，自然先去了解一下這個(gè)東西是什么東西

Chisel是什么？

Chisel（讀作[?t?i:z??l]），全名ConstructingHardwarein aScalaEmbeddedLanguage，是由伯克利開(kāi)發(fā)的硬件構(gòu)建語(yǔ)言，開(kāi)源。

官網(wǎng)：https://chisel.eecs.berkeley.edu/index.html

下面是官網(wǎng)上列出的一些特性：

硬件構(gòu)造語(yǔ)言（非HLS）

嵌入在Scala編程語(yǔ)言中

抽象的數(shù)據(jù)類型和接口

層次化+面向?qū)ο?功能化構(gòu)造

用Scala中的標(biāo)記來(lái)高度參數(shù)化

多時(shí)鐘域

大量的標(biāo)準(zhǔn)庫(kù)，包括浮點(diǎn)單元

針對(duì)ASIC和FPGA產(chǎn)生低層次的Verilog代碼

github開(kāi)源，BSD License

什么叫硬件構(gòu)建語(yǔ)言？是來(lái)代替Verilog/SystemVerilog的嗎？

Chisel可以簡(jiǎn)單的理解成高度抽象的、高度參數(shù)化的Verilog生成器，利用Scala語(yǔ)言的語(yǔ)法糖，來(lái)快速高效的開(kāi)發(fā)硬件設(shè)計(jì)。設(shè)計(jì)完成后，自動(dòng)生成Verilog，再經(jīng)由傳統(tǒng)的數(shù)字IC設(shè)計(jì)方法（邏輯綜合、APR）變成芯片。

我們注意幾點(diǎn)：

Chisel是基于Scala，也可以說(shuō)Chisel是用Scala語(yǔ)言寫的針對(duì)硬件開(kāi)發(fā)的庫(kù)。用Chisel語(yǔ)言做設(shè)計(jì)就是在寫Scala語(yǔ)言的程序。有點(diǎn)類似UVM是SystemVerilog語(yǔ)言的驗(yàn)證框架庫(kù)。

Chisel的應(yīng)用專注在前端設(shè)計(jì)，提高設(shè)計(jì)的效率。

生成的Verilog是低層次的，也就是類似門級(jí)的。

目前仍然通過(guò)DC或者Genus來(lái)綜合。

與HLS有明顯區(qū)別，不能直接變成工藝相關(guān)的門級(jí)電路。也許以后會(huì)增加這種功能，得看相關(guān)EDA的發(fā)展。

那Chisel相比Verilog有什么優(yōu)勢(shì)？

抽象程度高、高度參數(shù)化

前端設(shè)計(jì)周期縮短

可以走敏捷開(kāi)發(fā)流程

除了可以生成Verilog，還可以生成C/CPP。

都說(shuō)Chisel開(kāi)發(fā)快，那具體有哪些語(yǔ)法特性？

各種變量類型可以轉(zhuǎn)換

位寬可以自動(dòng)推斷

與Verilog一樣可以方便的取位和拼接

加減法可以防溢出

可以檢查敏感信號(hào)列表，防止生成latch

可以以黑盒子的方式調(diào)用Verilog，或者以in-line的方式嵌入Verilog

靈活高效的接口定義，再也不需要AUTOARG

可以定義多套不同的實(shí)現(xiàn)，比如FPGA和ASIC定義不同的RAM

可以處理多時(shí)鐘域，處理異步信號(hào)的同步

而這樣介紹Chisel：

Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language embedded in the high-level programming language Scala. At some point we will provide a proper reference manual, in addition to more tutorial examples. In the meantime, this document along with a lot of trial and error should set you on your way to using Chisel. Chisel is really only a set of special class definitions, predefined objects, and usage conventions within Scala, so when you write Chisel you are actually writing a Scala program that constructs a hardware graph. However, for the tutorial we don't presume that you understand how to program in Scala. We will point out necessary Scala features through the Chisel examples we give, and significant hardware designs can be completed using only the material contained herein. But as you gain experience and want to make your code simpler or more reusable, you will find it important to leverage the underlying power of the Scala language. We recommend you consult one of the excellent Scala books to become more expert in Scala programming.

首先Chisel是含于高級(jí)語(yǔ)言Scala之中，而且 Chisel實(shí)際上只是Scala中的一組特殊類定義，預(yù)定義對(duì)象和使用約定，因此當(dāng)您編寫Chisel時(shí)，您實(shí)際上正在編寫構(gòu)建硬件圖的Scala程序

Through the tutorial, we format commentary on our design choices as in this paragraph. You should be able to skip the commentary sections and still fully understand how to use Chisel, but we hope you'll find them interesting.

We were motivated to develop a new hardware language by years of struggle with existing hardware description languages in our research projects and hardware design courses. Verilog and VHDL were developed as hardware simulation languages, and only later did they become a basis for hardware synthesis. Much of the semantics of these languages are not appropriate for hardware synthesis and, in fact, many constructs are simply not synthesizable. Other constructs are non-intuitive in how they map to hardware implementations, or their use can accidently lead to highly inefficient hardware structures. While it is possible to use a subset of these languages and still get acceptable results, they nonetheless present a cluttered and confusing specification model, particularly in an instructional setting.

However, our strongest motivation for developing a new hardware language is our desire to change the way that electronic system design takes place. We believe that it is important to not only teach students how to design circuits, but also to teach them how to design circuit generators ---programs that automatically generate designs from a high-level set of design parameters and constraints. Through circuit generators, we hope to leverage the hard work of design experts and raise the level of design abstraction for everyone. To express flexible and scalable circuit construction, circuit generators must employ sophisticated programming techniques to make decisions concerning how to best customize their output circuits according to high-level parameter values and constraints. While Verilog and VHDL include some primitive constructs for programmatic circuit generation, they lack the powerful facilities present in modern programming languages, such as object-oriented programming, type inference, support for functional programming, and reflection.

Instead of building a new hardware design language from scratch, we chose to embed hardware construction primitives within an existing language. We picked Scala not only because it includes the programming features we feel are important for building circuit generators, but because it was specifically developed as a base for domain-specific languages.

對(duì)于如何使用Chisel表達(dá)

While Chisel focuses on binary logic, Chisel can support analog and tri-state wires with the Analog type - see Datatypes in Chisel.

We focus on binary logic designs as they constitute the vast majority of designs in practice. Tri-state logic are poorly supported standard industry flows and require special/controlled hard macros in order to be done.

在說(shuō)Chisel之前首先說(shuō)Scala語(yǔ)言，Scala是一門基于JVM運(yùn)行的語(yǔ)言，他與JAVA語(yǔ)言相互兼容，Scala也是一門面向?qū)ο蟮暮瘮?shù)式語(yǔ)言。

而現(xiàn)在對(duì)于主流的硬件描述語(yǔ)言還是Verilog，而Verilog一直以來(lái)也是有開(kāi)發(fā)效率低下的弊病。后來(lái)對(duì)于這個(gè)的問(wèn)題的討論結(jié)果是對(duì)Verilog進(jìn)行改良，也就出現(xiàn)了Verilog的后續(xù)標(biāo)準(zhǔn)——SystemVerilog，但是由于它只是用于驗(yàn)證。但是當(dāng)時(shí)除了改良還有一部分人主張把語(yǔ)言轉(zhuǎn)移到軟件語(yǔ)言，（C++、Java），支持C++的誕生了SystemC，而對(duì)于Chisel就是支持Java的那部分人創(chuàng)造出的

是由加州大學(xué)伯克利分校的研究團(tuán)隊(duì)發(fā)布的一種新型硬件語(yǔ)言。據(jù)團(tuán)隊(duì)成員之一Krste Asanovic教授介紹，早在30多年前還沒(méi)有硬件描述語(yǔ)言的時(shí)候，他們就已經(jīng)開(kāi)始構(gòu)想這樣一種語(yǔ)言了。最開(kāi)始Chisel是基于Ruby的，但是后來(lái)發(fā)現(xiàn)Scala更適合構(gòu)建Chisel。因?yàn)镾cala有諸多特性適合描述電路，比如它是靜態(tài)語(yǔ)言，以編譯期為主，適合轉(zhuǎn)換成Verilog/VHDL。再比如它的操作符即方法、柯里化、純粹的面向?qū)ο?、?qiáng)大的模式匹配、便捷的泛型編寫、特質(zhì)混入、函數(shù)式編程等特性，使得用Scala開(kāi)發(fā)DSL語(yǔ)言很方便。通過(guò)firrtl編譯器可以把Chisel文件轉(zhuǎn)換成firrtl文件，這是一種標(biāo)準(zhǔn)的中間交換格式，也就是讓各種高級(jí)語(yǔ)言方便地轉(zhuǎn)換到Verilog/VHDL的媒介，但它其實(shí)和verilog/VHDL屬于同一層次。在這里，Chisel選擇了妥協(xié)，沒(méi)有直接生成電路，而是借助Verilog，主要是因?yàn)闆](méi)有EDA工具支持，因此，它并不等同于HLS(High Level Synthesis)。將來(lái)也許會(huì)有EDA工具直接支持Chisel。