FPGA/IC領(lǐng)域術(shù)語表

FPGA/IC領(lǐng)域術(shù)語表

Chip Architecture芯片架構(gòu)

ADC: Analog to Digital Converter 模數(shù)轉(zhuǎn)換器

AES: Advanced encryption standard 高級(jí)加密標(biāo)準(zhǔn)

Adder: Circuit to add two numbers 將兩個(gè)數(shù)字相加的電路

ALU: Arithmetic logic unit 算術(shù)邏輯單元

Amdahl's Law: Amdahl's law of diminishing returns for speeding up fixed workloads 阿姆達(dá)爾定律-通過優(yōu)化系統(tǒng)的單個(gè)部分獲得的整體性能改進(jìn)受到實(shí)際使用改進(jìn)部分的時(shí)間分?jǐn)?shù)的限制

Arbiter: Arbitrates between competing requesters 仲裁器-在競爭請(qǐng)求者之間進(jìn)行仲裁

ASIC: Application specific integrated circuit.專用集成電路。

Audio codec: Device/program that compresses/decompresses digital audio 音頻編解碼器-壓縮/解壓縮數(shù)字音頻的設(shè)備/程序

Boolean algebra: Algebra in which variables are either true or false 布爾代數(shù)-變量為真或假的代數(shù)

BTB: Branch target buffer 分支目標(biāo)緩沖區(qū)

Cache: Local storage of program and/or data for future use. 程序和/或數(shù)據(jù)的本地存儲(chǔ)以供將來使用。

Cache coherence: Consistency of shared data that is stored in multiple local caches.存儲(chǔ)在多個(gè)本地緩存中的共享數(shù)據(jù)的一致性。

CAM: Content addressable memory 內(nèi)容可尋址存儲(chǔ)器

CISC: Complex instruction set computing 復(fù)雜指令集

Coprocessor: A processor used to supplement operations of a primary (host) processor.協(xié)處理器-用于補(bǔ)充主處理器操作的處理器。

CPI: Cycles per instruction 每條指令的周期

CPU: Central processing unit 中央處理器

CRC: Cyclic redundancy check 循環(huán)冗余校驗(yàn)

CSA: Carry save adder 進(jìn)位保存加法器

DAC: Digital to Analog Converter 數(shù)模轉(zhuǎn)換器

Distributed Computing: Computer with components working towards common goal with without strict coupling.分布式計(jì)算-具有朝著共同目標(biāo)工作的組件的計(jì)算機(jī)，沒有嚴(yán)格的耦合。

DLL: Delay locked loop 延遲鎖定環(huán)(DLL) 是一種類似于鎖相環(huán)(PLL) 的數(shù)字電路

DMA: Direct memory access 直接內(nèi)存訪問

DDR Double data rate 雙倍數(shù)據(jù)速率

DDS: Direct digital synthesis 直接數(shù)字合成

DSM: Distributed shared memory 分布式共享內(nèi)存

DSP: Digital signal processor 數(shù)字信號(hào)處理器

ECC: Error correcting code 糾錯(cuò)碼

Ethernet: Family of standard network technologies 標(biāo)準(zhǔn)網(wǎng)絡(luò)技術(shù)系列

Fault Tolerance: The ability of a system to keep operating in the event of failure of one of its components. 容錯(cuò)-系統(tǒng)在其組件之一發(fā)生故障的情況下保持運(yùn)行的能力。

FRAM: Non-volatile RAM based on ferroelectric layer.基于鐵電層的非易失性 RAM。

FPGA: Field-programmable gate array is a chip that can be reprogrammed "in the field". 現(xiàn)場可編程門陣列

FIFO: First in first out buffer 先進(jìn)先出緩沖區(qū)

GPU: Integrated circuit for accelerating the creation of graphics on a display. 圖形處理單元

DRAM: Dynamic random-access semiconductor memory 動(dòng)態(tài)隨機(jī)存取半導(dǎo)體存儲(chǔ)器

Flash: Non-volatile semiconductor memory 非易失性半導(dǎo)體存儲(chǔ)器

FFT: Fast Fourier transform 快速傅里葉變換

FPU: Floating point unit 浮點(diǎn)單元

GPIO: General purpose input output, controllable at run time 通用輸入輸出，運(yùn)行時(shí)可控

Gray code: Binary system where successive values differ by one bit 格雷碼：連續(xù)值相差一位的二進(jìn)制系統(tǒng)

HBM: High bandwidth memory 高帶寬內(nèi)存

I2C: Multi-master 2 wire bus 多主機(jī) 2 線總線

LAN: Local area network 局域網(wǎng)

LFSR: Linear feedback shift register 線性反饋移位寄存器

LSB: Least significant bit 最低有效位

[LUT] (https://en.wikipedia.org/wiki/Lookup_table): An array that replaces runtime computation with a simpler array indexing operation 查找表(LUT) 是一個(gè)數(shù)組，它用更簡單的數(shù)組索引操作代替運(yùn)行時(shí)計(jì)算。

LVDS: Low-voltage differential signaling (also TIA/EIA-644) 低壓差分信號(hào)（也是 TIA/EIA-644）

MII: Media independent interface for PHY chips PHY芯片的媒體獨(dú)立接口

MIMD: Multiple instructions multiple data architecture 多指令多數(shù)據(jù)架構(gòu)

MMU: Memory management unit 內(nèi)存管理單元

MSB: Most significant bit 最高有效位

MUX: Multiplexer 多路復(fù)用器

Multiplier: Binary multiplier 二進(jìn)制乘數(shù)

NCO: Numerically controlled oscillator 數(shù)控振蕩器

NOC: Network on a chip 片上網(wǎng)絡(luò)

Parallel Computing: A type of computation where many operations are carried out simultaneously. 并行計(jì)算

PCM: Phase change memory 相變存儲(chǔ)器

PCIe: High Speed serial computer expansion bus 高速串行計(jì)算機(jī)擴(kuò)展總線

PIC: Programmable interrupt controller 可編程中斷控制器

Priority Encoder: A circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs 優(yōu)先級(jí)編碼器-將多個(gè)二進(jìn)制輸入壓縮成較少數(shù)量輸出的電路或算法

PLL: Phase locked loop 鎖相環(huán)

PWM: Pulse width modulation脈沖寬度調(diào)制

Q: Q fixed point number formatQ 定點(diǎn)數(shù)格式

RAID: Redundant array of disks 冗余磁盤陣列

Reconfigurable Computing: Collection of customizable datapaths connected together by a fabric 可重構(gòu)計(jì)算-通過結(jié)構(gòu)連接在一起的可定制數(shù)據(jù)路徑的集合

RISC: Reduced instruction set computing 精簡指令集計(jì)算

ROM: Read only memory (denser than RAM) 只讀存儲(chǔ)器（比 RAM 更密集）

SBC: Single board computers 單板計(jì)算機(jī)

SDR: Software defined radio 軟件定義無線電

SERDES: Serializer/deserializer 串行器/解串器

Shift Register: Set of registers that shifts bits one position at a time 一次移位一個(gè)位置的一組寄存器

SIMD: Single instruction multiple data 單指令多數(shù)據(jù)

Schmitt Trigger: Comparator circuit with hysteresis 施密特觸發(fā)器-具有遲滯的比較器電路

SPI: Synchronous 4 wire master/slave interface 同步4線主/從接口

SRAM: Static random access semiconductor memory 靜態(tài)隨機(jī)存取半導(dǎo)體存儲(chǔ)器

TLB: Translation lookaside buffer 翻譯后備緩沖區(qū)

UART: Asynchronous 2 wire point to point interface 異步2線點(diǎn)對(duì)點(diǎn)接口

USB: 2 wire point to point 5 V interface 2線點(diǎn)對(duì)點(diǎn)5V接口

Video codec: Device/program that compresses/decompresses digital video 視頻編解碼器-壓縮/解壓縮數(shù)字視頻的設(shè)備/程序

Virtual Memory: The automatic mapping of virtual program addresses to physical addresses 虛擬內(nèi)存-虛擬程序地址到物理地址的自動(dòng)映射

VLIW: Very long instruction level parallelism 長的指令級(jí)并行性

WAN: Wide area network 廣域網(wǎng)

WIFI: Wireless local area network 無線局域網(wǎng)

8b10b: Code that maps 8-bits to 10bit DC balanced symbols 將 8 位映射到 10 位 DC 平衡符號(hào)的代碼

Chip Design芯片設(shè)計(jì)

Antenna effect: Plasma induced gate oxide damage that can occur during semiconductor processing. 天線效應(yīng)-在半導(dǎo)體加工過程中可能發(fā)生的等離子引起的柵極氧化物損壞。

Asynchronous logic: Logic not governed by a clock circuit or global clock. 異步邏輯-不受時(shí)鐘電路或全局時(shí)鐘控制的邏輯。

ATPG: Automatic test pattern generation 自動(dòng)測(cè)試模式生成

BIST: Built in Self Test 內(nèi)置自檢

Chip: A set of electronic circuits on one small plate ("chip") of semiconductor material, normally silicon. 芯片

Clock domain crossing: Traversal of signal in synchronous digital ssytem from one clock domain to another.時(shí)鐘域交叉-同步數(shù)字系統(tǒng)中的信號(hào)從一個(gè)時(shí)鐘域到另一個(gè)時(shí)鐘域的遍歷。

Clock gating: Technique whereby clock in synchronous logic is shut off when idle.門控時(shí)鐘-同步邏輯中的時(shí)鐘在空閑時(shí)關(guān)閉的技術(shù)。

CMOS: Complimentary metal-oxide semiconductor 互補(bǔ)金屬氧化物半導(dǎo)體

Cross talk: The coupling of nearby signals on a chip, usually through capacitive coupling. 串?dāng)_

CTS: Clock tree synthesis 時(shí)鐘樹合成

Domino logic: Fast clocked logic with reduced capacitive load 具有減少容性負(fù)載的快速時(shí)鐘邏輯

DEF: Design Exchange Format for layout 布局的設(shè)計(jì)交換格式

DFM: Extended DRC rules specifying how to make a high yielding design. 擴(kuò)展的 DRC 規(guī)則，指定如何進(jìn)行高產(chǎn)量設(shè)計(jì)。

DFT: Design for test可測(cè)試性設(shè)計(jì)或可測(cè)試性設(shè)計(jì)

Die: Small block of semiconductor material that can be cut ("diced") from a silicon wafer.可以從硅晶片上切割（“切塊”）的小塊半導(dǎo)體材料

DRC: Design Rule Constraints specifying manufacturing constraints. 指定制造約束的設(shè)計(jì)規(guī)則約束

DV: Design verification is the process of verifying that the logic design conforms to specification. 設(shè)計(jì)驗(yàn)證是驗(yàn)證邏輯設(shè)計(jì)是否符合規(guī)范的過程

ECO: Engineering change order 工程變更單

EDA: Electronic Design Automation tools used to enhance chip design productivity. 用于提高芯片設(shè)計(jì)生產(chǎn)力的電子設(shè)計(jì)自動(dòng)化工具

EDA companies: List of EDA companies EDA 公司

Electromigration: Transport of material caused by the gradual movement of the ions in a conductor. 由導(dǎo)體中的離子逐漸運(yùn)動(dòng)引起的物質(zhì)傳輸。

EMI: Electromagnetic interference. 電磁干擾

ESD: Electrostatic discharge is the sudden flow of electricity between two electrically charged objects. 靜電放電是兩個(gè)帶電物體之間的突然電流流動(dòng)

Fabless: The design and sale of semiconductor devices while outsourcing the manufacturing to 3rd party. 半導(dǎo)體設(shè)備的設(shè)計(jì)和銷售，同時(shí)將制造外包給第三方-無晶圓制造是硬件設(shè)備和半導(dǎo)體芯片的設(shè)計(jì)和銷售，同時(shí)將其制造（或晶圓廠）外包給稱為半導(dǎo)體代工廠的專業(yè)制造商.

FEOL: Front end of line processing. Includes all chip processing up to but not including metal interconnect layers. 生產(chǎn)線前端處理。包括所有芯片處理，但不包括金屬互連層。

Flip-flop: A clocked circuit that has two stable states and can be used to store state information. 觸發(fā)器

Foundry: Semiconductor company offering manufacturing services. 提供制造服務(wù)的半導(dǎo)體公司

Full custom design: Design methodology involving layout and interconnection of individual transistors. 完全定制設(shè)計(jì)-涉及各個(gè)晶體管的布局和互連的設(shè)計(jì)方法

GDSII: Binary format of design database sent to foundry. 發(fā)送制造廠的設(shè)計(jì)數(shù)據(jù)庫的二進(jìn)制格式

HDL: Specialized hardware description lanaguage for describing electronic circuits. 用于描述電子電路的專用硬件描述語言

Hold time: Minimum time synchronous input should hold steady after clock event. 時(shí)鐘事件后同步輸入應(yīng)保持穩(wěn)定的最短時(shí)間

IP: Semiconductor reusable design blocks containing author's Intellectual Property. 含作者知識(shí)產(chǎn)權(quán)的半導(dǎo)體可重復(fù)使用設(shè)計(jì)塊

IP Vendors: List of commercial semiconductor IP vendors. IP 供應(yīng)商

ISI: Intersymbol interference 符號(hào)間干擾( ISI ) 是一種信號(hào)失真形式，其中一個(gè)符號(hào)會(huì)干擾后續(xù)符號(hào)

Jitter: Deviation from perfect periodicity. 偏離完美的周期性

Latchup: Short circuit due to creation of a low-impedance path between the power supply rails of a circuit. 閂鎖-由于在電路的電源軌之間創(chuàng)建低阻抗路徑而引起的短路

Layout: Physical representation of an integrated circuit. 布局-集成電路的物理表示

LEF: Standard Cell Library Exchange Format layout.標(biāo)準(zhǔn)單元庫交換格式布局。

Logical Effort: Technique used to normalize (and optimize) digital circuits speed paths. Logical Effort是Ivan Sutherland和Bob Sproull在 1991 年創(chuàng)造的一個(gè)術(shù)語，是一種用于估計(jì)CMOS電路延遲的簡單技術(shù)

LVS: Layout Versus Schematic software checks that the layout is identical to the netlist.LVS : Layout Versus Schematic 軟件檢查布局是否與網(wǎng)表相同。

Mask Works: Copyright law dedicated to 2D and 3D integrated circuit "layouts". “掩模工作”-專門針對(duì) 2D 和 3D 集成電路“布局”的版權(quán)法。

Mealy machine: A finite state machine whose outputs depend on current state and the current inputs. 一種有限狀態(tài)機(jī)，其輸出取決于當(dāng)前狀態(tài)和當(dāng)前輸入。

Metastability: Ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium. 數(shù)字電子系統(tǒng)在不穩(wěn)定平衡中持續(xù)無限時(shí)間的能力。

MLS: Packaging and handling precautions for some semiconductors. 濕氣敏感度級(jí)別與某些半導(dǎo)體的包裝和處理注意事項(xiàng)有關(guān)。MSL 是針對(duì)濕度敏感設(shè)備可暴露于室內(nèi)環(huán)境條件（1 級(jí)為 30 °C/85%RH；所有其他級(jí)別為 30 °C/60%RH）的時(shí)間段 的電子標(biāo)準(zhǔn)。

Moore Machine: Finite state machine whose outputs depend only on its current state.Moore型有限狀態(tài)機(jī)，其輸出僅取決于其當(dāng)前狀態(tài)。

Moore's Law: Observation by Moore that the number of transistors in an IC doubles approximately every two years. 摩爾定律-摩爾觀察到，IC 中的晶體管數(shù)量大約每兩年翻一番。

MOSFET: Metal oxide field effect transistor. 金屬氧化物場效應(yīng)晶體管。

MOSIS: Foundry service project offering MPWs and low volume manufacturing. 提供MPW和小批量制造的鑄造服務(wù)項(xiàng)目。

MPW: Multi-project wafer service that integrates multiple designs on one reticle (aka "shuttle"). 多項(xiàng)目芯片( MPC ) 和多項(xiàng)目晶圓( MPW ) 半導(dǎo)體制造安排允許客戶在多個(gè)設(shè)計(jì)或項(xiàng)目之間共享掩模和微電子 晶圓制造成本

MTBF: Mean time between failures. 平均故障間隔時(shí)間。

Multi-threshold CMOS: CMOS technology with multiple transistor types with different threshold voltages. 多閾值 CMOS：具有不同閾值電壓的多種晶體管類型的 CMOS 技術(shù)。

Optical proximity correction: Technique used to compensate for semiconductor diffraction/process effects. 光學(xué)鄰近校正-用于補(bǔ)償半導(dǎo)體衍射/工藝效應(yīng)的技術(shù)。

Pass Transistor Logic: Logic that connects input to non-gate terminal of mosfet transistor. 將輸入連接到mosfet晶體管的非柵極端子的邏輯

Physical design: Physical design flow ("layout").物理設(shè)計(jì)流程（“布局”）。

PDK: Process design kits consisting of a minimum set of files needed to design in a specific process. 流程設(shè)計(jì)工具包，包含在特定流程中進(jìn)行設(shè)計(jì)所需的最少文件集

Power gating: Technique used to reduce leakage/standby power by shutting of the supply to the circuit. 電源門控：用于通過關(guān)閉電路電源來減少泄漏/待機(jī)功率的技術(shù)

P&R: Automated Place and Route of a circuit using an EDA tool. 使用 EDA 工具自動(dòng)布局和布線電路

PVT Corners: Represents the extreme process, voltage, temperature that could occur in a given semiconductor process. 表示給定半導(dǎo)體工藝中可能出現(xiàn)的極端工藝、電壓、溫度

Radiation Hardening: Act of making devices resistant to damage caused by ionizing radiation. 輻射硬化是使電子元件和電路能夠抵抗由高水平電離輻射（粒子輻射和高能電磁輻射）引起的損壞或故障的過程

RTL: Design abstraction for digital circuit design. 寄存器傳輸級(jí)( RTL ) 是一種設(shè)計(jì)抽象，它根據(jù)硬件寄存器之間的數(shù)字信號(hào)（數(shù)據(jù)）流以及對(duì)這些信號(hào)執(zhí)行 的邏輯操作對(duì)同步 數(shù)字電路進(jìn)行建模

Setup time: Minimum time synchronous input should be ready before clock event. 建立時(shí)間-最小時(shí)間同步輸入應(yīng)在時(shí)鐘事件之前準(zhǔn)備好

SEU: Change of state caused by one single ionizing particle (ions, electrons, photons...). 由單個(gè)電離粒子（離子、電子、光子......）引起的狀態(tài)變化

Signoff: The final approval that the design is ready to be sent to foundry for manufacturing. signoff（也寫為sign-off ）檢查是設(shè)計(jì)在流片之前必須通過的一系列驗(yàn)證步驟的總稱

SOC: System On Chip 片上系統(tǒng)

Spice: Open source analog electronic circuit simulator. 開源模擬電子電路模擬器

STA: Method of computing the expected timing of a digital circuit without requiring full circuit simulation. 靜態(tài)時(shí)序分析(STA)

Standard Cell Design: Design process relying on a fixed set of standard cells. 標(biāo)準(zhǔn)單元設(shè)計(jì)-設(shè)計(jì)過程依賴于一組固定的標(biāo)準(zhǔn)單元

Subthreshold Leakage: Current between source and drain in MOSFET when transistor is "off". 亞閾值泄漏-晶體管“關(guān)閉”時(shí) MOSFET 源極和漏極之間的電流

Synchronous logic: Logic whose state is controlled by a synchronous clock. 同步邏輯

Synthesis: Translation of high level design description (e.g. Verilog) to a netlist format (e.g. standard cell gate level). 綜合-將高級(jí)設(shè)計(jì)描述（例如 Verilog）轉(zhuǎn)換為網(wǎng)表格式（例如標(biāo)準(zhǔn)單元門級(jí)）

SystemC: Set of C++ classes and macros for simulation. Commonly used for high level modeling and testing. 一組用于模擬的 C++ 類和宏。常用于高級(jí)建模和測(cè)試

Tape-out: Act of sending photomask chip database ("layout") to the manufacturer. 流片：將光掩模芯片數(shù)據(jù)庫（“布局”）發(fā)送給制造商的行為。

TCL: Scripting language used by most of the leading EDA chip design tools. 大多數(shù)領(lǐng)先的 EDA 芯片設(shè)計(jì)工具使用的腳本語言。

Transistor: A semiconductor device used to amplify/switch electronic signals. 晶體管

Verilog: The dominant hardware description language (HDL) for chip design. 用于芯片設(shè)計(jì)的主要硬件描述語言 (HDL)

VLSI: Very large Integrated Circuit (somewhat outdated term, everything is VLSI today). 大的集成電路（有點(diǎn)過時(shí)的術(shù)語，今天一切都是 VLSI）

Von Neumann architecture: Computer architecture in which instructions and data are stored in the same memory. 馮諾依曼架構(gòu)：指令和數(shù)據(jù)存儲(chǔ)在同一內(nèi)存中的計(jì)算機(jī)架構(gòu)。

Manufacturing制造業(yè)

BEOL: Back end of line processing for connecting together devices using metal interconnects. 使用金屬互連將設(shè)備連接在一起的生產(chǎn)線后端處理。

Dicing: Act of cutting up wafer into individual dies. 切割-將晶圓切割成單個(gè)裸片的行為

FinFet: Non planar, double-gate transistor. 非平面雙柵晶體管

Photo-lithography: Process used in micro-fabrication to pattern parts of a thin film or the bulk of a substrate. 光刻：用于微制造的工藝，用于對(duì)薄膜的部分或基板的主體進(jìn)行圖案化。

Photomasks: Opaque plates with holes or transparencies that allow light to shine through in a defined pattern. 光掩模：帶有孔或透明膠片的不透明板，可讓光線以規(guī)定的圖案透過。

Reticle: A set of photomasks used by a stepper to step and print patterns onto a silicon wafer.標(biāo)線：步進(jìn)機(jī)使用的一組光掩模，用于在硅晶片上步進(jìn)和打印圖案。

Semiconductor Fabrication: Process used to create the integrated circuits. 半導(dǎo)體制造：用于制造集成電路的工藝。

Silicon: Element (Si), forms the basis of the electronic revolution. 硅：元素 (Si)，構(gòu)成電子革命的基礎(chǔ)。

Silicon on insulator: Layered silicon–insulator–silicon with reduced parasitic capacitance. 絕緣體上硅：具有降低寄生電容的層狀硅-絕緣體-硅。

Stepper: Machine that passes light through reticle onto the silicon wafer being processed. 步進(jìn)器：將光通過標(biāo)線板傳遞到正在處理的硅晶片上的機(jī)器。

TSV: Vertical electrical connection (via) passing completely through a silicon wafer or die. 硅通孔( TSV ) 或芯片通孔是完全穿過硅晶片或芯片的垂直電連接(通孔)。

Wafer: Thin slice of semiconductor material used in electronics for the fabrication of integrated circuits. 晶片：用于制造集成電路的電子器件中的半導(dǎo)體材料薄片。

Wafer thinning: Wafer thickness reduction to allow for stacking and high density packaging. 晶圓減?。壕A厚度減小以允許堆疊和高密度封裝。

Packaging封裝

3D IC's: The process of stacking integrated circuits and connecting them through TSVs. 通過堆疊硅晶片或裸片并使用例如硅通孔(TSV) 或 Cu-垂直互連

BGA: Ball grid array is a type of surface-mount packaging (a chip carrier) used for integrated circuits. 球柵陣列是一種用于集成電路的表面貼裝封裝（芯片載體）

BGA substrate: A miniaturized PCB that mates the silicon die to BGA pins. 將硅芯片與 BGA 引腳配對(duì)的小型化 PCB

Bumping: Placing of bumps on wafer/dies in preparation for package assembly. 凸塊：在晶圓/裸片上放置凸塊，為封裝組裝做準(zhǔn)備。

DIMM: Dual in line memory module. 雙列直插內(nèi)存模塊。

Flip-chip: Method of bonding a silicon die to package using solder bumps. 使用焊料凸點(diǎn)將硅芯片鍵合到封裝上的方法。

IC Assembly: Semiconductor die is encased in a supporting case "package". IC 組裝

Interposer: Electrical interface used to spread a connection to a wider pitch. 用于將連接擴(kuò)展到更寬間距的電氣接口

Heat sink: A passive heat exchanger. 散熱器-被動(dòng)式熱交換器。

Heat pipe: Device for efficiently transferring heat between two solid interfaces . 熱管-在兩個(gè)固體界面之間有效傳遞熱量的裝置。

KGD: Known Good Die. Dies that have been completely tested at wafer probe. 晶圓測(cè)試是半導(dǎo)體器件制造過程中執(zhí)行的一個(gè)步驟。在此步驟中，在將晶圓發(fā)送到芯片準(zhǔn)備之前執(zhí)行，晶圓上存在的所有單個(gè)集成電路都通過對(duì)其應(yīng)用特殊的測(cè)試模式來測(cè)試功能缺陷。

Leadframe: Metal structure inside a chip package that carry signals from the die to the outside. 引線框架：芯片封裝內(nèi)的金屬結(jié)構(gòu)，可將信號(hào)從芯片傳送到外部。

POP: Package on Package

SIP: System In Package 系統(tǒng)封裝

SMT: Technique whereby packaged chips are mounted directly onto the PCB surface. 封裝芯片安裝在 PCB 表面上的技術(shù)。

Through-hole: TPackage pins inserted in drilled holes and soldered on opposite side of the board. 通孔

Wirebond: Method of bonding a silicon die to a package using wires. 使用導(dǎo)線將硅芯片與封裝結(jié)合的方法

WSI: Wafer scale integration 晶圓級(jí)集成

Test測(cè)試

Arbitrary Waveform Generator: Electronic instrument used to generate arbitrary signal waveforms. 任意波形發(fā)生器：用于產(chǎn)生任意信號(hào)波形的電子儀器。

ATE: Automatic Test Equipment for testing integrated circuits. 用于測(cè)試集成電路的自動(dòng)測(cè)試設(shè)備。

Burn-in: Process of screening parts for potential premature life time failures. 老化：篩選零件以發(fā)現(xiàn)潛在的過早壽命故障的過程。

DIB: Device Interface Board for interfacing DUT to ATE. Also called DUT board, probe card, load board, PIB. 用于將 DUT 連接到 ATE 的設(shè)備接口板。也稱為 DUT 板、探針卡、負(fù)載板、PIB。

DMM: Electronic instrument for measuring voltage, current, and resistance. 用于測(cè)量電壓、電流和電阻的電子儀器。

DUT: Device under test 被測(cè)設(shè)備

FIB: Focused ion beam 聚焦離子束

JTAG: Industry standard for verifying and testing/debugging printed circuit boards after manufacturing. 制造后驗(yàn)證和測(cè)試/調(diào)試印刷電路板的行業(yè)標(biāo)準(zhǔn)。

Logic Analyzer: Electronic instrument for capturing multiple digital signal from a system. 邏輯分析儀：用于從系統(tǒng)中捕獲多個(gè)數(shù)字信號(hào)的電子儀器。

MCM: Multi-chip Module 多芯片模塊

Oscilloscope: Electronic instrument for tracking the change of an electrical signal over time. 示波器：跟蹤電信號(hào)隨時(shí)間變化的電子儀器。

Probe Card: A direct interface between electronic test systems and a semiconductor wafer. 探針卡：電子測(cè)試系統(tǒng)和半導(dǎo)體晶片之間的直接接口。

SEM: Scanning electron microscope 掃描電子顯微鏡

Shmoo Plot: An ASCII plot of a component response over a range of conditions. Shmoo 圖：在一系列條件下組件響應(yīng)的 ASCII 圖。

Spectrum Analyzer: Electronic instrument for measuring the power of the spectrum of an unknown signal. 頻譜分析儀：用于測(cè)量未知信號(hào)頻譜功率的電子儀器。

審核編輯 ：李倩