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活動(dòng)簡介

作為三星SAFE生態(tài)系統(tǒng)的重要合作伙伴之一，芯和半導(dǎo)體將于2023年6月27日-28日參加三星Foundry 論壇及SAFE論壇2023美國站（SFF & SAFE Forum 2023）的活動(dòng)。

在三星Foundry論壇中, 參與者能獲得三星的遠(yuǎn)景規(guī)劃及最新的技術(shù)創(chuàng)新，并聆聽來自頂級(jí)技術(shù)專家和行業(yè)領(lǐng)袖嘉賓的演講。在三星 SAFE 論壇中, 您還將了解到三星SAFE合作伙伴分享的行業(yè)趨勢(shì)及在EDA, IP, DSP, 及Packaging領(lǐng)域的挑戰(zhàn)和解決方案，了解高性能計(jì)算和汽車領(lǐng)域的先進(jìn)設(shè)計(jì)解決方案，并在展館通過與SAFE合作伙伴的討論和合作，拓寬對(duì)行業(yè)趨勢(shì)和創(chuàng)新技術(shù)的見解。

技術(shù)演示

芯和半導(dǎo)體將在此次大會(huì)上帶來多項(xiàng)技術(shù)演示，包括：

Metis：先進(jìn)封裝SI/PI分析

Metis為3DIC Chiplet先進(jìn)封裝提供了完整的SI/PI/多物理場分析解決方案，支持包括三星I-Cube, H-Cube, R-Cube, X-Cube在內(nèi)的眾多主流先進(jìn)封裝工藝。

Metis多尺度能力和容量優(yōu)勢(shì)能支持“裸芯片、中介層和基板“統(tǒng)一的 EM 仿真，突破了借助傳統(tǒng)工具“剪切再縫合”方法帶來的易錯(cuò)性和局限性。它的多模式分析選項(xiàng)為工程師提供了速度和精確性的選擇，滿足了從架構(gòu)探索到最終簽核的各個(gè)設(shè)計(jì)環(huán)節(jié)對(duì)仿真效率和精度的不同需求。

Metis在半導(dǎo)體行業(yè)國際在線平臺(tái)3D InCites的最新評(píng)選中勝出，獲封2023“Herb Reiter 年度最佳設(shè)計(jì)工具供應(yīng)商獎(jiǎng)”稱號(hào)。

IRIS：先進(jìn)工藝制程下的片上無源建模與仿真

芯和半導(dǎo)體射頻設(shè)計(jì)平臺(tái)支持從芯片、封裝、模組到板級(jí)的射頻全鏈路設(shè)計(jì)，包括射頻系統(tǒng)設(shè)計(jì)工具XDS、片上射頻及高速無源抽取工具IRIS、PDK建模及驗(yàn)證工具iModeler/iVerifier；IPD包括各種標(biāo)準(zhǔn)和定制集成無源器件及芯片電容等。

IRIS在三星多項(xiàng)先進(jìn)工藝節(jié)點(diǎn)上獲得認(rèn)證，包括三星8nm LPP FinFET 工藝及28FDS FD-SOI 工藝。憑借加速的3D EM求解器，先進(jìn)工藝支持以及與Virtuoso的無縫集成，IRIS能幫助RF IC設(shè)計(jì)人員實(shí)現(xiàn)首次設(shè)計(jì)即能成功的硅上體驗(yàn)。

大會(huì)議程

Samsung Foundry Forum Program:

Date:June 27th, 2023

Time:12:00 - 5:30pm PDT

Venue:Signia by Hilton San Jose, Imperial Ballroom

Address:170 S. Market St., San Jose, CA 95113

Time	R/T(min)	Program
12:00 - 13:00	60’	Networking Lunch & Registration
13:00 - 13:05	5’	Opening(Jinman Han, EVP & Head of DSA Office, Samsung Electronics)
13:05 - 13:20	15’	Samsung Keynote(Siyoung Choi,President,Foundry Business, Samsung Electronics)
13:20 - 13:35	15’	“An Energy Efficient Future of AI”(Joe Macri, SVP, CTO of Computing & Graphics, AMD)
13:35 - 13:50	15’	“Meeting System User Demands in a Slowing Moore’s Law Era” (Chidi Chidambaram, Fellow, Technology and Foundry Engineering, Qualcomm)
13:50 - 14:05	15’	Break
14:05 - 14:35	30’	Process Technology(Gitae Jeong, EVP & Head of Technology Development, Samsung Electronics)
14:35 - 14:50	15’	Manufacturing Excellence (Sang Sup Jeong, EVP & Head of Manufacturing Technology, Samsung Electronics)
14:50 - 15:10	20’	Design Platform (Jongwook Kye, EVP & Head of Design Platform Development, Samsung Electronics)
15:10 - 15:25	15’	Sustainability(Claire Seo, VP, DS Corporate Sustainability Management, Samsung Electronics)
15:25 - 15:40	15’	Break
15:40 - 15:55	15’	“RiscV, AI, and the Next Generation of Compute” (Jim Keller, President & CEO, Tenstorrent)
15:55 - 16:15	20’	Advanced Heterogeneous Integration (Moonsoo Kang, EVP & Head of AVP Business Team, Samsung Electronics)
16:15 - 16:35	20’	Business & Customers (Sang-Pil Sim, EVP & Head of Foundry Worldwide Sales & Marketing, Samsung Electronics)
16:35 - 16:40	5’	Closing (Marco Chisari, EVP & Head of U.S. Foundry and SSIC, Samsung Electronics)
16:40 - 17:30	50’	Partner Pavilion & Networking

SAFEForum Program:

Date:June 28th, 2023

Time:9:00am - 5:30pm PDT

Venue:Signia by Hilton San Jose, Imperial Ballroom & Regency Ballroom 1

Address:170 S. Market St., San Jose, CA 95113

Time	R/T(min)	Program
09:00 - 10:00	60’	Registration
10:00 - 10:05	5’	Opening (Jinman Han, EVP & Head of DSA Office, Samsung Electronics)
10:05 - 10:15	10’	Welcoming Remarks (Jongwook Kye, EVP & Head of Design Platform Development, Samsung Electronics)
10:15 - 10:35	20’	“The 3Ps of 3D-ICs” (Ajei Gopal, President & CEO, Ansys)
10:35 - 10:55	20’	“Unleashing a New Era of Compute with Chiplet-Powered Silicon” (Tony E. Pialis, President & CEO, Alphawave Semi)
10:55 - 11:15	20’	“High-Performance Design in Samsung Foundry” (Leon Stok, VP, IBM)
11:15 - 11:35	20’	Samsung Foundry Process & Business Update (Gibong Jeong, EVP & Head of Business Development, Samsung Electronics)
11:35 - 11:50	15’	Break
11:50 - 12:50	60’	Lunch (Partner Pavilion & Networking)
12:50 - 13:00	10’	Break
13:00 - 16:15	195’	[Tech Session I] Advanced Technology and Design Infrastructure	[Tech Session II] Advanced Design Solutions for HPC and Automotive
Tech Talk: Sangyun Kim, VP & Head of Design Technology, Samsung Electronics Room: Imperial Ballroom Presenter: 8 partner presentations ADT, Ansys, ARM, Cadence, Synopsys	Tech Talk: Jongshin Shin, EVP & Head of IP Ecosystem, Samsung Electronics Room: Regency Ballroom 1 Presenter: 8 partner presentations Alphawave, Cadence, CoAsia, Samsung AVP, SemiFive, Siemens, Synopsys
16:15 - 16:30	15’	Closing	Closing
16:30 - 17:30	60’	Partner Pavilion & Networking

審核編輯：湯梓紅

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