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ST公司的ST8500是全可編動力線通信（PLC）調制解調器片上系統(tǒng)（SoC），采用標準ARM? 32-bit Cortex?-M4F全可編程核，可以運行任何的PLC協(xié)議如ITU G.9904（PRIME），ITU G.9903 （G3-PLC?），目標CENELEC EN50065， FCC和ARIB兼容的應用，集成了差分PLC模擬前端，包括具有自動增益控制和PGA和ADC，帶發(fā)送預驅動器的DAC，數字發(fā)送電平控制，零交叉比較器和高達500kHz PLC信號帶寬，最高工作頻率高達200MHz，工作溫度-40℃到+105℃，主要用在智能計量，智能電網和物聯(lián)網（IoT），以及和CENELEC， FCC 與 ARIB兼容的應用設計。本文介紹了ST8500主要特性，框圖和詳細架構圖以及評估板EVALKITST8500-1主要特性，框圖，電路圖，材料清單和PCB設計圖。

The ST8500 is a fully programmable power line communication （PLC） modem System onChip （SoC）， able to run any PLC protocol in the frequency band up to 500 kHz.

The device architecture has been designed to target CENELEC EN50065， FCC and ARIBcompliant applications supporting all major PLC protocol standards such as ITU G.9904（PRIME）， ITU G.9903 （G3-PLC?） and many other possible PLC protocol specifications andevolutions.

ST8500主要特性：

? Programmable power line communication（PLC） modem System on Chip

? Integrated differential PLC analog front-end

– PGA with automatic gain control and ADC

– DAC with transmission pre-driver

– Digital transmission level control

– Zero crossing comparator

– Up to 500 kHz PLC signal bandwidth

? High performance， fully programmable realtimeengine dedicated to PLC PHY and real -time MAC protocol management （400 MHzmax. frequency）

– Dedicated code and data SRAM memories

? Standard ARM? 32-bit Cortex?-M4F fullyprogrammable core for protocol upper layersand peripherals management

– 200 MHz maximum frequency

– 256 kB of embedded SRAM for code anddata

– 96 kB of embedded SRAM for data

– 8 kB of embedded shared RAM

– Bootloader ROM memory

– One Time Programmable （OTP） memorywith dedicated areas available for securekeys and user information storage

– Serial wire and JTAG interfaces

– 24 multiplexed GPIOs

– 4 general purpose timers

– 1 flexible CRC calculation unit

– 2 USART， 1 UART， 3 SPI， 1 I2C

? Cryptographic engine

– AES 128/192/256 engine

– True random number generator

– Pseudo random number generator

? Clock management：

– 25 MHz external crystal for system clock

– Integrated 25 MHz oscillator （XOSC） withfrequency synthesizer （FS） andpre-scalerunits to generate internal clock signals

? Power management

– 3.3 V external supply voltage for I/O andanalog

– 2.5 V internal linear regulator for analog

– 1.1 V external supply voltage for digital

– Normal， Slow， Doze and low power modes

? Available in QFN56 package

? -40℃ to +105℃ temperature range

ST8500應用：

? Smart metering， smart grid and Internet ofThings applications

? Suitable for application design compliant withCENELEC， FCC and ARIB regulations

[原創(chuàng)] ST ST8500全可編PLC調制解調器片上系統(tǒng)(SoC)開發(fā)方案

圖1.ST8500基本框圖

The ST8500 architecture is composed of the following parts：

1. PLC front-end including digital front-end （DFE） and analog front-end （AFE）

2. Real-time engine： the digital core running the lower layers of the PLC protocol stackand implementing modulation， demodulation and advanced forward error corrections（FEC） algorithms

3. Protocol engine： the digital core running the upper layers of the PLC protocol stack andmanaging the interface with external microcontrollers.

4. Peripherals， crypto， debug section

5. Clock and reset section

6. Power management section

[原創(chuàng)] ST ST8500全可編PLC調制解調器片上系統(tǒng)(SoC)開發(fā)方案

圖1.ST8500詳細架構圖

評估板EVALKITST8500-1

The EVALKITST8500-1 is a platform which allows an easy way to evaluate the features andperformance of a power line communication （PLC） node based on the ST8500 modemsystem-on-chip and the STLD1 line driver.

This user manual explains the EVALKITST8500-1 hardware and software installation， anddetails the evaluation of the kits.

This user manual does not explain the functionalities of the various PLC protocols runningon the ST8500. Detailed information can be found in the protocol specific documentation，available within the software packages， separately delivered under the Software licenseagreement by contacting your local ST sales office.

[原創(chuàng)] ST ST8500全可編PLC調制解調器片上系統(tǒng)(SoC)開發(fā)方案