| Function | Deserializer |
| Color depth (bpp) | 18 |
| Input compatibility | FPD-Link LVDS |
| Pixel clock frequency (Max) (MHz) | 43 |
| Output compatibility | LVCMOS |
| Features | Low-EMI Point-to-Point Communication |
| EMI reduction | LVDS |
| Diagnostics | BIST |
| Operating temperature range (C) | -40 to 105 |
- Supports Displays With 18-Bit Color Depth
- 5-MHz to 43-MHz Pixel Clock
- Automotive-Grade Product AEC-Q100 Grade 2
Qualified - 24:1 Interface Compression
- Embedded Clock With DC Balancing Supports
AC-Coupled Data Transmission - Capable to Drive up to 10 Meters Shielded
Twisted-Pair Cable - No Reference Clock Required (Deserializer)
- Meets ISO 10605 ESD – Greater than 8 kV HBM
ESD Structure - Hot Plug Support
- EMI Reduction – Serializer Accepts Spread
Spectrum Input; Data Randomization and
Shuffling on Serial Link; Deserializer Provides
Adjustable PTO (Progressive Turnon) LVCMOS
Outputs - @Speed BIST (Built-In Self-Test) to Validate
LVDS Transmission Path - Individual Power-Down Controls for Both
Transmitter and Receiver - Power Supply Range 3.3 V ±10%
- 48-Pin TQFP Package for Transmitter and 64-Pin
TQFP Package for Receiver - Temperature Range: –40°C to 105°C
- Backward-Compatible Mode With
DS90C241/DS90C124
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI?s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
