基于Slice的總線宏的簡易設(shè)計

針對傳統(tǒng)的實(shí)現(xiàn)FPGA局部動態(tài)可重構(gòu)中總線宏的設(shè)計方法比較復(fù)雜的問題，提出了一種Virtex-5 FPGA局部動態(tài)重構(gòu)中基于Slice的總線宏的簡易設(shè)計方法。在介紹總線宏基本原理的基礎(chǔ)上，分析傳統(tǒng)設(shè)計方法的復(fù)雜性，結(jié)合Virtex-5芯片的結(jié)構(gòu)特點(diǎn)，以Xilinx的ISE9.1i和PlanAhead9.2.7開發(fā)軟件為依托，通過宏文件獲取、模塊例化和連線以及放置總線宏來實(shí)現(xiàn)總線宏的設(shè)計。實(shí)驗(yàn)和仿真結(jié)果表明，該方法簡單易行、靈活性強(qiáng)，能夠工程化應(yīng)用于Virtex-5 FPGA的局部動態(tài)重構(gòu)設(shè)計中。

Abstract:

?Aiming at the problem that the traditional method of designing and realization the bus macro in FPGA dynamic partial reconfiguration was complicated， a facility method to design the Virtex-5 FPGA bus macro based on Slice-based was proposed. On the basis of introducing bus macro basic principle， the complexity of the traditional design methods was analyzed. Combined with the characteristic of Virtex-5 chip， relied on the Xilinx’ISE9.1i and PlanAhead9.2.7 software， the design of bus macro was realized by getting the macro file，module implement and connecting leads as well as placing the bus macro. The results of experiment and simulation show that this method is sinrple， praticable and flexible， which can be applied to Virtex-5 FPGA dynamic partial reconfiguration’s designing.