資料介紹
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH2T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH2T45 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input.
The SN74AVCH2T45 is designed so that the DIR input is powered by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
NanoFree? package technology is a major breakthrough in IC packaging concepts, using the die as the package.
- 具有可配置電平移位和轉換以及3態(tài)輸出的2位2電源總線收發(fā)器SN74AVCH2T45數(shù)據(jù)表
- SN74AVC2T45-Q1,pdf(Dual-Bit Du
- SN74LVC2T45,pdf(Dual-Bit Dual-
- SN74AVCH8T245,pdf(8-BIT DUAL-S
- SN74AVCH4T245,pdf(4-Bit Dual-S
- SN74AVCH32T245,pdf(32-BIT DUAL
- SN74AVCH24T245,pdf(24-BIT DUAL
- SN74AVCH20T245,pdf(20-BIT DUAL
- SN74AVCH16T245,pdf(32-BIT DUAL
- SN74AVC2T45,pdf(DUAL-BIT DUAL-
- SN74AVC2T245,pdf(Dual-Bit Dual
- SN74LVCH16901,pdf(18-Bit Unive
- SN74ALVCH16901,pdf(18-BIT UNIV
- SN74AUC2G66,pdf(DUAL BILATERAL
- SN74LV8154,pdf(DUAL 416-BIT BI
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