基于i.MX286應(yīng)用處理器勘誤表

　　Currently， software checks the active bit in dTD to see whether it is finished. If the Active bit is 0，

　　then software frees the allocated memory for the dTD.

　　The hardware sequence after all data of a dTD is transferred is as follows：

　　1. Update the dTD. This includes an AHB write access of three DWords. The active bit is cleared

　　in the first DW write.

　　2. Update the qHead （this includes an AHB write access of three DWords）。

　　3. Read the dTD again to check if software added a new dTD （this is a SINGLE AHB read）。 At

　　the same time， send out an interrupt if needed.

　　After step 1， if software finds the Active bit is cleared， then the dTD memory space is freed and

　　may be allocated for another thread’s use. In step 3， hardware may get a wrong dTD.

　　This issue does not occur if some delay is added before freeing the dTD memory space.

　　This issue only occurs in USB INCR8 mode， because steps 1 and 2 have 6 SINGLE AHB transfers

　　in INC8 mode， but only two burst AHB transfers in INCR mode.

　　This issue only occurs when the dTD list is used; because if only one dTD is used， the software

　　only checks the Active bit after an interrupt is received （step 3）。 However， when the dTD list is

　　used， the software may check the entire list after the interrupt for the first dTD is received， when

　　the hardware has just finished the transfer of the second dTD.