基于FPGA/CPLD的LED/LCD通用顯示譯碼器設(shè)計

基于FPGA/CPLD的LED/LCD通用顯示譯碼器設(shè)計
Design of Commonly Used LED/LCD Display Decoder Based on FPGA/CPLD

摘要:各種數(shù)字系統(tǒng)的終端設(shè)備都需要對十進(jìn)制信息進(jìn)行數(shù)碼顯示，而LED和LCD是最常用的顯示器件。在大規(guī)?？?a target='_blank' class='arckwlink_none'>編程邏輯器件FPGA與CPLD的硬件基礎(chǔ)上，根據(jù)顯示譯碼器原理運(yùn)用VHDL硬件描述語言對LED/LCD的通用七段顯示譯碼器進(jìn)行了設(shè)計，同時使用QUARTUS 1開發(fā)軟件對設(shè)計電路進(jìn)行了時序仿真和功能驗證。此設(shè)計在大規(guī)模數(shù)字電路的數(shù)碼顯示中更為實(shí)用，具有設(shè)計簡單、使用靈活和工作可靠等優(yōu)點(diǎn)。
關(guān)鍵詞:譯碼器仿真VHDL描述數(shù)字電路脈沖信號
Abstract; Digital display of decimal information is needed for all kinds of terminal equipments of digital systems, and LED and LCD are the most common display devices. On the hardware basis of large-scale programmable logical devices FPGA and CPLD, and by using hardware description language VHDL, the seven-segment display decoder for LED/LCD is designed. In addition, with QUARTUS 11 developing software,the timing simulation and functional verification of the designed circuit are carried out. The design can be used practicaly in digital display of large-scale digital circuits. This device features simple design, flexible and reliable operation.
Keywords;D ecoder Simulation VHDLd escription Digitalc ircuit Pulses ignal