FPGA教程之頻率簡(jiǎn)介

FPGA教程之頻率簡(jiǎn)介

每個(gè)CPU都有一個(gè)工作頻率，F(xiàn)PGA也不例外（當(dāng)然，只有你的設(shè)計(jì)應(yīng)該是時(shí)序邏輯），那該頻率是根據(jù)什么形成的呢？

首先，我們來(lái)分析16-bit計(jì)數(shù)器，通過(guò)該用例，掌握QuartusII的時(shí)序分析器及了解一個(gè)時(shí)序邏輯頻率的概念。源代碼如下（QuautusII7.2SP3，EP2C35F484C8）：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

?

entity counter is

port(

?????????? rst:??????????????????????????????? in? std_logic;

?????????? clk:??????????????????????????????? in? std_logic;

?????????? carry:??????????????????????????? out std_logic

?????????? );

end counter;

?

architecture synlogic of counter is

signal r_cnt:?????????????????????????? std_logic_vector(15 downto 0);

begin

process(rst, clk)

begin

?????????? if rst = '1' then

??????????????????? r_cnt <= (others => '0');

?????????? elsif rising_edge(clk) then

??????????????????? r_cnt <= r_cnt + '1';

?????????? end if;

end process;

carry <= '1' when r_cnt = X"FFFF" else '0';

end synlogic;

建立工程，將所有的輸入輸出管腳分配為Virtual Pin，其中時(shí)鐘管腳Virtual Pin Clock，表示該工程沒(méi)有實(shí)際輸入輸出管腳，方法如下：

單擊菜單Assignments/Assignment Editor，打開(kāi)窗口Assignment Editor；

然后，右鍵“To”列下的“《new》”，選擇“Node Finder…”；

其次，單擊“List”，選擇“Carry”，“clk”，“rst”到右邊的“Selected Nodes”，單擊OK返回；

而后，在Assignment Name下面分別選擇“Virtual Pin”，“Virtual Pin Clock”，“Virtual Pin”，并且在Value列下都選擇“On”，保存；

最后，對(duì)其進(jìn)行全編譯；

觀察“Compilation Report/Timing Analyzer/Clock Setup：‘clk’”， Fmax從小到大排列，取其中最小的Fmax值，得Fmax = 293.86MHz，則表示該十六位計(jì)數(shù)器最快可以運(yùn)行在293.86MHz。那該頻率主要是受什么因素影響？首先，我們先看Fmax的定義，在QuartusII的幫助中有如下說(shuō)明：

The maximum clock frequency that can be achieved without violating internal setup (tSU) and hold (tH) time requirements. Unrestricted fMAX is the maximum frequency at which a design can run. Restricted fMAX is the maximum frequency a design can run considering device limits, such as maximum toggle rates. The Classic Timing Analyzer analyzes and reports fMAX following timing analysis.

You can specify the fMAX required by default for a design in the Classic Timing Analysis Settings page of the Settings dialog box. You can also specify the required fMAX of individual clock signals in a design by creating clock settings and assigning them to signals in the design.

The Classic Timing Analyzer calculates fMAX with the following equation:

fMAX = 1/( - + + )

Clock skew delay is calculated with the following equation:

- ，即Tcd2 – Tcd1。

從表達(dá)式可以知道，F(xiàn)max主要受以下四個(gè)因素影響：register to register delay/寄存器到寄存器延時(shí)Tnet，clock skew delay/寄存器間時(shí)鐘偏斜，micro setup delay/LC中的D觸發(fā)器建立時(shí)間Tsetup，micro clock to output delay/ LC中的D觸發(fā)器時(shí)鐘輸出延時(shí)Tcko。如下圖：

下面，我們具體計(jì)算一下293.86MHz的得出：

選中第一行，點(diǎn)擊右鍵選擇“List Paths”，觀察QuartusII底部的Messages窗口：

Inf Clock "clk" has Internal fmax of 293.86 MHz between source register "r_cnt[0]" and destination register "r_cnt[15]" (period= 3.403 ns)

Inf + Longest register to register delay is 3.139 ns

Inf - Smallest clock skew is 0.000 ns

Inf + Micro clock to output delay of source is 0.304 ns

Inf + Micro setup delay of destination is -0.040 ns

具體路徑如下：

1、?? 最長(zhǎng)寄存器與寄存器之間延遲為3.139ns

2、?? 時(shí)鐘偏斜為0ns

3、?? 時(shí)鐘輸出延遲(即時(shí)鐘到達(dá)D觸發(fā)器到數(shù)據(jù)Q輸出)為0.304ns

4、?? D觸發(fā)器建立時(shí)間-0.040ns(參考CycloneII的Datasheet)，這里是由器件特性決定的，也就是說(shuō)數(shù)據(jù)可以早到達(dá)40ps

所以Fmax = 1/[3.139 + 0.304 + (-0.0040) - 0.000] ns= 293.86MHz。

通過(guò)以上描述，大致了解了FPGA中Fmax的參數(shù)的定義及計(jì)算方式，也了解了QuartusII中的時(shí)序分析工具Classic Timing Analyzer。需要注意的是，F(xiàn)max只對(duì)同步邏輯進(jìn)行分析，如果對(duì)應(yīng)設(shè)計(jì)為異步邏輯設(shè)計(jì)，則該數(shù)據(jù)沒(méi)有意義。