FPGA中的多時鐘域設計

覺得這篇文章很好，因此在這里翻譯一下——或者也可以說是按我的理解加中文注釋。

Multiple, independent clocks are ubiquitous in system-on-chip (SoC) design. Most SoC devices have multiple interfaces, some following standards that use very different clock frequencies.
在一個SOC設計中，存在多個、獨立的時鐘，這已經是一件很平常的事情了。大多數的SOC器件都具有很多個接口，各個接口標準都可能會使用完全不同的時鐘頻率。

Many modern serial interfaces are inherently asynchronous from the rest of the chip; some actually derive their clocks directly from the incoming data streams. There is also a trend toward designing major sub-blocks of SoCs to run on independent clocks to ease the problem of clock skew across large chips.
例如對于現(xiàn)代的串行通信接口而言，它們自然而然地就與芯片的其余部分是不同步的，因為它們的時鐘有時候就是直接從數據流中恢復出來的。而且，現(xiàn)在還有一個趨勢，就是有時候為了在避免大芯片中令人頭痛的所謂"clocl skew"問題，索性讓各個子模塊都具有獨立的時鐘。

For all of these reasons, designers working on SoC projects are virtually certain to encounter multiple clocks and to be faced with the design of logic interconnecting two portions of the chip running on independent clocks. Each such portion is known as a clock domain. The interface between logic on different clocks is called a clock domain crossing or clock domain boundary. The proper handing of signals across clock domain boundaries is critical for successful SoC design.
因為以上原因，進行SOC設計時，常常要考慮工作在不同時鐘下的兩個部分邏輯之間的互連問題，而每個部分，都可稱之為“時鐘域”，連接它們之間的那部分數字邏輯可稱為“時鐘邊界”或所謂“跨時鐘域”。合理地處理跨時鐘的問題，對于一個成功的SOC設計來說非常關鍵。

Problem #1: Meta-stability

The first multi-clock problem that designers must consider is that of meta-stability as signals pass from one clock domain to another. Most designers understand that meta-stability is a real problem in real circuits; the modern abstractions of RTL design and static timing analysis can't entirely shield designers from having to worry about the underlying physics.
1) 亞穩(wěn)態(tài)
多時鐘域設計的第一個問題，便是信號從一個時鐘域傳輸到另一個時鐘域的時候，可能會出現(xiàn)亞穩(wěn)態(tài)。 許多設計者都知道，在真實的電路中的確會存在所謂亞穩(wěn)態(tài)的問題。但是，在現(xiàn)代的FPGA設計中，即使設計者面對的是RTL級抽象和靜態(tài)時序分析，卻仍然不能完全將這個問題拒之門外，因為抽象的掩蓋之下，我們仍然避免不了真實的物理規(guī)律。

Whenever a signal enters a clocked circuit element, such as a flip-flop, too close to the clock, there is the potential for meta-stability. When this happens, the flip-flop may not immediately settle to a known value. It is critical that the output signal from the flip-flop not be used until it has settled.
任何時候，一個信號輸入到一個時鐘觸發(fā)的電路——例如一個D觸發(fā)器，當信號(跳變)過于靠近時鐘前沿，便會存在所謂亞穩(wěn)態(tài)問題。這個時候，DFF的輸出端不會馬上產生一個可預知的值，也就是說，在這段時間內，輸出信號是無效的。

On a truly asynchronous clock boundary, the receiving domain's clock is used to capture each signal from the driving domain in a flip-flop. Because there is no defined temporal relationship between the clock and the signal, it is entirely possible that they could transition at the same time. Whenever this happens, there is a possibility of meta-stability in the receiving clock domain.
在設計中，常常會用一個觸發(fā)器接收來自于另一個時鐘域的輸出信號(即用本地時鐘的前沿來鎖存另一個時鐘域的信號）。由于觸發(fā)器的時鐘和數據輸入信號不存在確定的相位關系，因此完全有可能出現(xiàn)數據和時鐘同時跳變的情況。這樣，就在接收端所在的時鐘域中造成了亞穩(wěn)態(tài)。

This is not just a theoretical potential. GHz-rate chips with clocking design errors can exhibit the effects of meta-stability quite quickly when running in real systems. These effects typically include loss of critical handshake signals between clocks domains, and corruption of multi-bit data"serious problems that are highly likely to require a chip re-spin.
亞穩(wěn)態(tài)的風險，并不僅僅是理論上的。對于GHz數據率的芯片，如果時鐘設計考慮不當，一旦把它放到實際系統(tǒng)中運行，亞穩(wěn)態(tài)的效果所造成的危害很快就會表現(xiàn)出來。最典型的比如說，跨時鐘域的關鍵握手信號丟失，以及并行數據出錯。然后這個芯片的設計很可能就泡湯，于是你不得不推倒重來。(所謂 re-spin，按我的理解，是重新開始的意思)

Most designers also know that the textbook solution to meta-stability is using two levels of flip-flops on each signal crossing a clock domain boundary. Even if the first flip-flop does become meta-stable, there is an extremely high likelihood that the signal will settle by the time that it passes through the second level. The double-level flip-flop structure is often called a synchronizer, and designers commonly speak of synchronizing signals across clock domains.
多數設計者都已經知道，對于亞穩(wěn)態(tài)，教科書上經典的解決辦法，就是在凡時鐘邊界的地方，都用兩級(D)觸發(fā)器對信號進行同步。這樣的話，哪怕第一級D觸發(fā)器進入了亞穩(wěn)態(tài)，后一級也極有可能把它克服掉。這種兩級觸發(fā)器結構，通常稱為“synchronizer”，這個過程也稱為跨時鐘域信號同步。

Problem #2: Reset synchronization 復位的同步問題
Improper synchronization of reset signals is a related problem in multi-clock designs. Designers sometimes forget that reset signals are subject to meta-stability and must be protected by synchronizers. Generally, the entire SoC can be reset by a single signal, which therefore must propagate to all clocked elements in all clock domains.
復位信號的不同步，也是一個與多時鐘設計相關的問題。設計者有時候會忘了一個事實，那就是復位信號也可能引起亞穩(wěn)態(tài)問題，而且必須用synchronizers來對它進行同步。通常來說，每個SOC都會有一個reset信號，這個信號被送到各個時鐘域的各個同步邏輯單元，來對整個芯片/系統(tǒng)進行復位。

There is no need for synchronization on the activation edge of reset, since by definition all state elements are reset to initial values, and the reset signal will generally be held active for enough cycles to allow any meta-stability to settle out.