Xilinx Spartan6 IO 電平讀書筆記

FPGA的IO支持多種電平標(biāo)準(zhǔn),但是其中用幾點(diǎn)的概念比較模糊,在此特意記下:

最近在用xilinx的spartan 6 與ARM進(jìn)行通信，但是FPGA的邏輯電平是3.3V的LVTTL標(biāo)準(zhǔn),而ARM輸出的是1.8V的電平標(biāo)準(zhǔn)，兩者IO電平的不匹配，出現(xiàn)了一些問題如下：

FPGA在VCCO = 3.3V是，是否可以設(shè)置FPGA的IO電平標(biāo)準(zhǔn)為1.8V？

在翻閱了《Spartan-6 FPGA SelectIO Resources》后，得到了以下信息：Spartan-6的供電來源于3個(gè)引腳：VCCINT、VCCO、VCCAUX。

VCCINT is the main power supply for the internal FPGA logic. VCCINT also powers some of the available input drivers.

VCCINT主要為FPGA的內(nèi)部邏輯單元供電，同時(shí)也會給一些輸入供電。

The VCCO supplies, one for each of the I/O banks,power the output drivers and some of the input drivers. The voltage on the VCCO pins determines the voltage swing of the output signal.

Many of the low-voltage I/O standards supported by Spartan-6 devices require adifferent output drive voltage (VCCO). As a result, each device often supportsmultiple output drive source voltages.

Output buffers within a given VCCO bank must share the same output drivesource voltage. The following I/Ostandards input buffers also use the VCCO voltage supply:

? LVCMOS25 (when VCCAUX = 3.3V)

? LVCMOS18_JEDEC

? LVCMOS15_JEDEC

? LVCMOS12_JEDEC

? PCI

? MOBILE_DDR

Spartan-6 FPGAs allow multiple I/Ostandards to be combined in the same device. Although the outputs are always powered byVCCO, multiple standards are available

under one of the five possible VCCO values. In addition, inputs often do notneed to match the voltage applied to VCCO. Further flexibility is achieved withmultiple VCCO levels in a single device.

Each bank of I/Os has independent VCCO and VREF rails. This allows each bank to be powered at VCCO and VREF levels independent of how the other banksare set. VCCO provides power primarily to the I/O outputbuffers, and VREF supplies a reference voltage for HSTL and SSTL inputs. The VCCO pins are dedicated power pins and must bepowered at all times with a voltage rail from thePCB. However, the VREF pins are dual-purpose pins; they can be used as regular I/O pinsor VREF-supply pins. When a bank uses VREF-powered inputs (as an example, for the SSTL or HSTL standards), thedesign must use the VREF pins to supply the FPGA’s internal VREF rail with the reference voltage. If the SSTL or HSTL inputs are not used in a bank,the VREF pins in that bank can be used as regular I/O pins. Table 1-5 lists the VCCO and VREF requirements.

VCCO在FPGA中，每個(gè)Bank都有自己獨(dú)立的VCCO，每個(gè)Bank的VCCO可以供不同的電源，以實(shí)現(xiàn)不同的Bank實(shí)現(xiàn)不同的IO標(biāo)準(zhǔn)，在同一個(gè)Bank中，VCCO只能是一個(gè)標(biāo)準(zhǔn)，通過上面的解釋中，可以看到，IO的輸出都是由VCCO供電的，也就是說每個(gè)Bank的IO輸出電壓決定于VCCO，同時(shí)部分標(biāo)準(zhǔn)的輸入也是由VCCO提供電源的。在一個(gè)Bank中，輸入的IO標(biāo)準(zhǔn)是可以不與VCCO相匹配的，如下圖所示，VCCO為3.3V時(shí)，輸入LVCMOS18的標(biāo)準(zhǔn)同樣可以識別！

由此可見，對于3.3v的VCCO，輸出的電平標(biāo)準(zhǔn)只能是3.3V，但是輸入的標(biāo)準(zhǔn)可以是1.8V。