基本組合邏輯功能雙向管腳的Verilog HDL源代碼

　　電子發(fā)燒友網(wǎng)核心提示：本例程是Verilog HDL源代碼：關(guān)于基本組合邏輯功能中雙向管腳的功能實(shí)現(xiàn)源代碼。
Verilog HDL: Bidirectional Pin

This example implements a clocked bidirectional pin in Verilog HDL.
The value of OE determines whether bidir is an input, feeding in inp, or a tri-state, driving out the value b.

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

input?? oe;
input?? clk;
input?? [7:0] inp;
output? [7:0] outp;
inout?? [7:0] bidir;

reg???? [7:0] a;
reg???? [7:0] b;

assign bidir = oe ? a : 8'bZ ;
assign outp? = b;

// Always Construct

always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end

endmodule